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M48Z08 M48Z18
64 Kbit (8Kb x 8) ZEROPOWER(R) SRAM
INTEGRATED ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY UNLIMITED WRITE CYCLES READ CYCLE TIME EQUALS WRITE CYCLE TIME AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48Z08: 4.50V VPFD 4.75V - M48Z18: 4.20V VPFD 4.50V SELF-CONTAINED BATTERY in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28 LEAD SOIC and SNAPHAT(R) TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY PIN and FUNCTION COMPATIBLE with the DS1225 and JEDEC STANDARD 8K x 8 SRAMs DESCRIPTION The M48Z08/18 ZEROPOWER(R) RAM is an 8K x 8 non-volatile static RAM which is pin and functional compatible with the DS1225. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory solution. Table 1. Signal Names
A0-A12 DQ0-DQ7 E G W VCC VSS March 1999 Address Inputs Data Inputs / Outputs Chip Enable Output Enable
SNAPHAT (SH) Battery
28
28 1
1
PCDIP28 (PC) Battery CAPHAT
SOH28 (MH)
Figure 1. Logic Diagram
VCC
13 A0-A12 M48Z08 M48Z18
8 DQ0-DQ7
W E G
VSS
Write Enable Supply Voltage Ground 1/18
AI01022
M48Z08, M48Z18
Figure 2A. DIP Pin Connections Figure 2B. SOIC Pin Connections
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
28 1 27 2 26 3 25 4 24 5 23 6 7 M48Z08 22 M48Z18 21 8 20 9 19 10 18 11 17 12 13 16 14 15
AI01183
VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 28 27 2 26 3 25 4 24 5 23 6 7 M48Z18 22 21 8 20 9 19 10 18 11 17 12 16 13 15 14
AI01023B
VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TSLD
(2)
Parameter Ambient Operating Temperature Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation
Value -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1
Unit C C C V V mA W
VIO VCC IO PD
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO 4.75V to 5.5V or 4.5V to 5.5V VCC E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2/18
M48Z08, M48Z18
Figure 3. Block Diagram
A0-A12
LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY
POWER
8K x 8 SRAM ARRAY
DQ0-DQ7
VPFD
E W G
VCC
VSS
AI01394
DESCRIPTION (cont'd) The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28 pin 600mil DIP CAPHATTM houses the M48Z08/18 silicon with a long life lithium button cell in a single package. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel form.
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 30pF
CL includes JIG capacitance
AI01398
3/18
M48Z08, M48Z18
Table 5. Capacitance (1, 2) (TA = 25 C)
Symbol CIN CIO
(3)
Parameter Input Capacitance Input / Output Capacitance
Test Condition VIN = 0V VOUT = 0V
Min
Max 10 10
Unit pF pF
Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected
Table 6. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI
(1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V
Min
Max 1 5 80 3 3
Unit A A mA mA mA V V V V
ILO
ICC ICC1 ICC2 VIL
(2)
-0.3 2.2 IOL = 2.1mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4
VIH VOL VOH
Notes: 1. Outputs deselects. 2. Negative spikes of -1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C)
Symbol VPFD VPFD VSO tDR Parameter Power-fail Deselect Voltage (M48Z08) Power-fail Deselect Voltage (M48Z18) Battery Back-up Switchover Voltage Expected Data Retention Time 11 Min 4.5 4.2 Typ 4.6 4.3 3.0 Max 4.75 4.5 Unit V V V YEARS
Note: 1. All voltages referenced to VSS.
DESCRIPTION (cont'd) For the 28 lead SOIC, the battery package (i.e. SNAPHAT) part number is "M4Z28-BR00SH1". The M48Z08/18 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data until valid power returns.
4/18
M48Z08, M48Z18
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70C)
Symbol tPD tF
(1) (2)
Parameter E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD(min) to VPFD (max) VCC Rise Time VSO to VPFD (min) VCC Rise Time E or W at VIH after Power Up
Min 0 300 10 0 1 1
Max
Unit s s s s s ms
tFB
tR tRB tREC
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD INPUTS
RECOGNIZED
tDR tFB tRB DON'T CARE
tR tREC
NOTE RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systems may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/18
M48Z08, M48Z18
Table 9. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z08 / M48Z18 Symbol Parameter Min tAVAV tAVQV
(1)
-100 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
100 100 100 50 10 5 50 40 5
ns ns ns ns ns ns ns ns ns
tELQV (1) tGLQV tELQX tGLQX
(1) (2) (2)
tEHQZ (2) tGHQZ tAXQX
(2) (1)
Notes: 1. CL = 100pF (see Figure 4). 2. CL = 30pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV A0-A12 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI01385
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
6/18
M48Z08, M48Z18
Table 10. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z08 / M48Z18 Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tE1HDX tWLQZ
(1, 2)
-100 Max
Unit
Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition
100 0 0 80 80 10 10 50 30 5 5 50 80 80 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tAVWH tAVEH tWHQX (1, 2)
Notes: 1. CL = 30pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
READ MODE The M48Z08/18 is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48Z08/18 is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
7/18
M48Z08, M48Z18
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01386
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01387B
tELEH
tEHAX
8/18
M48Z08, M48Z18
DATA RETENTION MODE With valid VCC applied, the M48Z08/18 operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z08/18 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48Z08/18 for an accumulated period of at least 11 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus tREC (min). E should be kept high as VCC rises past VPFD(min) to prevent inadvertent write cycles prior to system stabilization. Normal RAM operation can resume tREC after VCC exceeds VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. SYSTEM BATTERY LIFE The useful life of the battery in the M48Z08/18 is expected to ultimately come to an end for one of two reasons: either because it has been discharged while providing current to the RAM in the battery back-up mode, or because the effects of aging render the cell useless before it can actually be completely discharged. The two effects are virtually unrelated, allowing discharge or Capacity Consumption, and the effects of aging or Storage Life, to be treated as two independent but simultaneous mechanisms. The earlier occurring failure mechanism defines the battery system life of the M48Z08/18.
Figure 9. Predicted Battery Storage Life versus Temperature
AI01399
50 40 30 20 t1% t50% (AVERAGE)
10
YEARS
8 6 5 4 3 2
1 20 30 40 50 60 70 80 90
TEMPERATURE (Degrees Celsius)
9/18
M48Z08, M48Z18
Cell Storage Life Storage life is primarily a function of temperature. Figure 9 illustrates the approximate storage life of the M48Z08/18 battery over temperature. The results in Figure 9 are derived from temperature accelerated life test studies performed at SGSTHOMSON. For the purpose of the testing, a cell failure is defined as the inability of a cell stabilized at 25C to produce a 2.4V closed circuit voltage across a 250 k load resistor. The two lines, t1% and t50%, represent different failure rate distributions for the cell's storage life. At 70C, for example, the t1% line indicates that an M48Z08/18 has a 1% chance of having a battery failure 28 years into its life while the t50% shows the part has a 50% chance of failure at the 50 year mark. The t1% line represents the practical onset of wear out and can be considered the worst case Storage Life for the cell. The t50% can be considered the normal or average life. Calculating Storage Life The following formula can be used to predict storage life:
1 {[(TA1/TT)/SL1]+[(TA2/TT)/SL2]+...+[(TAN/TT)/SLN]}
Reference for System Life Each M48Z08/18 is marked with a nine digit manufacturing date code in the form of H99XXYYZZ. For example, H995B9431 is: H = fabricated in Carrollton, TX 9 = assembled in Muar, Malaysia, 9 = tested in Muar, Malaysia, 5B = lot designator, 9431 = assembled in the year 1994, work week 31. POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 10) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 10. Supply Voltage Protection
where, - TA1, TA2, TAN = time at ambient temperature 1, 2, etc. - TT = total time = TA1+TA2+...+TAN - SL1, SL2, SLN = storage life at temperature 1, 2, etc. For example, an M48Z08/18 is exposed to temperatures of 55C or less for 8322 hrs/yr, and temperatures greater than 60C but less than 70C for the remaining 438 hrs/yr. Reading predicted t1% values from Figure 9, - SL1 200 yrs, SL2 = 28 yrs - TT = 8760 hrs/yr - TA1 = 8322 hrs/yr, TA2 = 438 hrs/yr Predicted storage life
1 {[(8322/8760)/200]+[(431/8760)/28]}
VCC VCC
or 154 years. As can been seen from these calculations and the results, the expected lifetime of the M48Z08/18 should exceed most system requirements. Estimated System Life Since either storage life or capacity consumption can end the battery's life, the system life is marked by which ever occurs first.
0.1F
DEVICE
VSS
AI02169
10/18
M48Z08, M48Z18
ORDERING INFORMATION SCHEME
Example:
M48Z18
-100 MH
1
TR
Supply Voltage and Write Protect Voltage 08 (1) VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V 18 VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V
Speed -100 100ns PC MH
Package PCDIP28
(2,3)
Temp. Range 1 6
(4)
Shipping Method for SOIC blank Tubes TR Tape &Reel
0 to 70 C -40 to 85 C
SOH28
Notes: 1. The M48Z08 part is offered with the PCDIP28 (i.e. CAPHAT) package only. 2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number "M4Z28-BR00SH1" in plastic tube or "M4Z28-BR00SH1TR" in Tape & Reel form. 3. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are functionally equivalent (see package drawing section for details). 4. Temperature range available for M48Z18 product only. Caution: Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since this will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
11/18
M48Z08, M48Z18
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N mm Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ inches Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Drawing is not to scale.
12/18
M48Z08, M48Z18
SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT
Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 mm Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ inches Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing not to scale.
13/18
M48Z08, M48Z18
SOH28 - 28 lead Plastic Small Outline, 2-socket battery SNAPHAT
Symb Typ A A1 A2 B C D E e eB H L N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 mm Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ inches Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-B
Drawing not to scale.
14/18
M48Z08, M48Z18
SH - 4-pin SNAPHAT Housing for 49 mAh Battery
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 mm Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ inches Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
A1
A2 A A3
eA D
B eB
L
E
SH
Drawing not to scale.
15/18
M48Z08, M48Z18
SH - 2-pin SNAPHAT Housing for 49 mAh Battery
Symb Typ A A1 A2 A3 B D E eB L 0.46 21.21 14.22 3.20 2.03 6.73 6.48 mm Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 3.61 2.29 0.018 0.835 0.560 0.126 0.080 0.265 0.255 Typ inches Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.142 0.090
A1
A2 A A3
B D eB
L
E
SHZP-A
Drawing not to scale.
16/18
M48Z08, M48Z18
SH - 2-pin SNAPHAT Housing for 130 mAh Battery
Symb Typ A A1 A2 A3 B D E eB L 0.46 21.21 17.27 3.20 2.03 8.00 7.24 mm Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 3.61 2.29 0.018 0.835 0.680 0.126 0.080 0.315 0.285 Typ inches Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.142 0.090
A1
A2 A A3
B D eB
L
E
SHZP-B
Drawing not to scale.
17/18
M48Z08, M48Z18
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved (R) TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics TM CAPHAT and BYTEWIDE are trademarks of STMicroelectronics All other names are the property of their respective owners STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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